The present invention relates to methods and tools, such as electronic design automation (EDA) tools, for designing systems cm a target device.
EDA or computer aided design (CAD) tools are used for designing systems on integrated circuits (ICs). Examples of ICs include application specific integrated circuits (ASICs) and programmable logic devices (PLDs) (which are also sometimes referred to as complex PLDs (CPLDs), programmable array logic (PALs), programmable logic arrays (PLAs), field PLAs (FPLAs), erasable PLDs (EPLDs), electrically erasable PLDs (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), or by other names).
A process of designing a system on a target device using EDA or CAD tools may include the following: design entry, synthesis, technology mapping, placement, and routing. Synthesis often includes retiming, which is also sometimes referred to as register retiming. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve the maximum operating frequency (fmax) of the system.
Register retiming during synthesis is relatively easy to accomplish because it is relatively easy to move gates (i.e., logic devices in the system) and registers at that early stage of the design process. However, register retiming during synthesis also has the following disadvantage. Delay estimates during synthesis are less accurate than during later stages. This is partly because the distance between devices plays an important role in determining delay and there is less information regarding this distance during the synthesis stage than at later stages of the design process.
Retiming, such as register retiming, may also occur during later stages of the design process, such as placement. One advantage of register retiming at this stage is that delay estimates are better known than at earlier stages. However, there are also disadvantages associated with register retiming during placement. First, moving gates and registers is relatively more difficult during placement than during earlier stages of the design process. Second, it is computationally more intensive because of the requirement for incremental compilation associated with the incremental placement resulting from register retiming at the placement stage.